Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array including memory strings, each of the memory strings including a first select transistor, first dummy cells, memory cells, second dummy cells connected in series and a second select transistor, the first dummy cells being arranged between the first select transistor and the memory cells, the second dummy cells being arranged between the memory cells and the second select transistor;
• word lines connected to the memory cells;
• first dummy word lines connected to the first dummy cells;
• second dummy word lines connected to the second dummy cells;
• and
• a row decoder configured to drive the word lines, the first dummy word lines, and the second dummy word lines,
• the row decoder comprising first hookup transistors connected to the word lines, first dummy hookup transistors connected to the first dummy word lines, and second dummy hookup transistors connected to the second dummy word lines,
• wherein a group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistors, and the second dummy hookup transistors is aligned on either of one row and rows, and
• the first dummy hookup transistors and the second dummy hookup transistors are arranged at least at one end of the group of hookup transistors.

A semiconductor memory device comprising:

• a memory cell array including memory strings, each of the memory strings including a first select transistor, a first dummy cell, memory cells, a second dummy cell, and a second select transistor connected in series, the first dummy cell being arranged between the first select transistor and the memory cells, the second dummy cell being arranged between the memory cells and the second select transistor;
• word lines connected to the memory cells;
• a first dummy word line connected to the first dummy cell;
• a second dummy word line connected to the second dummy cell;
• and
• a row decoder configured to drive the word lines, the first dummy word line, and the second dummy word line,
• the row decoder comprising first hookup transistors connected to the word lines, a first dummy hookup transistor connected to the first dummy word line, and a second dummy hookup transistor connected to the second dummy word line,
• wherein a group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows,
• the first dummy hookup transistor and the second dummy hookup transistor are arranged at least at one end of the group of hookup transistors, and
• second hookup transistors, which have a high resistance against a surrounding environment, of the first hookup transistors are arranged adjacent to the first dummy hookup transistor and the second dummy hookup transistor.