P-channel 3d memory array

A method for inducing hot electron injection in a selected memory cell in a p-channel NAND string in a NAND array, comprising:

• applying a program bias arrangement to program a selected memory cell, the program bias arrangement including:
• a positive program voltage pulse on a word line coupled with a selected memory cell, blocking flow of carriers between a first semiconductor body region on a first side of the selected memory cell and a second semiconductor body region on a second side of the selected memory cell;
• a negative drain side pass voltage pulse on word lines in the plurality of word lines on the first side of the selected memory cell;
• a negative source side pass voltage on word lines in the plurality of word lines on the second side of the selected memory cell;
• and
• bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell during the negative drain side pass voltage pulse thereby causing capacitive boosting of the first semiconductor region to a boosted, negative voltage level, and to allow current flow between a source line and the semiconductor body region on the second side of the selected memory cell thereby coupling the semiconductor body on the second side of the selected memory cell to the source line.

A memory comprising:

• a 3D NAND array including a plurality of NAND strings, a NAND string in the array including a plurality of p-channel memory cells arranged in series in an n-type semiconductor body;
• a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells;
• and
• control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line using a program bias arrangement that induces band-to-band tunneling hot electron injection.

A memory comprising:

• a 3D NAND array including a plurality of NAND strings, a NAND string in the array including a plurality of p-channel memory cells arranged in series in an n-type semiconductor body;
• a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells;
• and
• control circuitry coupled to the plurality of word lines adapted for selectively erasing a selected memory cell in the plurality of memory cells using a selective erase bias arrangement to reduce a threshold in the selected memory cell.