Shift register unit, shift register circuit, array substrate and display device

A shift register circuit, comprising a plurality of shift register units connected in cascade,

• each of the shift register units comprising:
• a capacitor having two electrodes, a first electrode of the two electrodes being connected with an output terminal;
• a first transistor, a gate thereof being connected with a signal input terminal, a drain thereof being connected with a first level terminal, and a source thereof being connected with a second electrode of the capacitor;
• a second transistor, a gate thereof being connected with a resetting terminal, a drain thereof being connected with the source of the first transistor, and a source thereof being connected with a second level terminal;
• a third transistor, a gate thereof being connected with the source of the first transistor, a drain thereof being connected with a first clock signal terminal, and a source thereof being connected with the output terminal;
• a fourth transistor, a gate thereof being connected with a second clock signal terminal, a drain thereof being connected with the output terminal, and a source thereof being connected with a low level terminal;
• a fifth transistor, a drain thereof being connected with the drain of the second transistor, and a source thereof being connected with the low level terminal;
• a sixth transistor, a gate thereof being connected with a gate of the fifth transistor, a drain thereof being connected with the drain of the fourth transistor, and a source thereof being connected with the source of the fourth transistor;
• a voltage pulling-down control module connected with the second clock signal terminal, the low level terminal, the gate of the fifth transistor, the source of the first transistor, a frame start signal terminal and a third level terminal, wherein in the case that the frame start signal terminal and the third level terminal of the voltage pulling-down module are at high levels simultaneously, the voltage pulling-down control module outputs a high level at the gate of the fifth transistor, and the fifth transistor is in a turn-on state so as to pull down a gate voltage of the third transistor, and the sixth transistor is also in the turn-on state so as to pull down a voltage at the output terminal,
• wherein, except for a first shift register unit and a last shift register unit of the plurality of shift register units connected in cascade, the output terminal of each of the remaining shift register units is connected with the signal input terminal of the next shift register unit adjacent thereto, the resetting terminal of each of the remaining shift register units is connected with the output terminal of the next shift register unit adjacent thereto, and the frame start signal terminal of each of the remaining shift register units being connected with the respective third level terminal,
• the third level terminal of the first shift register unit being connected with the second level terminal, the resetting terminal of the first shift register unit being connected with the output terminal of the next shift register unit adjacent thereto, and the third level terminal of the last shift register unit being connected with the first level terminal.

A display device, comprising:

• a display area having a plurality of pixels for displaying an image;
• a shift register circuit for transferring a scanning signal to the display area;
• and
• a data driving circuit for transferring a data signal to the display area.
• wherein the shift register circuit comprises a plurality of shift register units connected in cascade, and each of the shift register units comprising:
• a capacitor having two electrodes, a first electrode of the two electrodes is connected with an output terminal;
• a first transistor, a gate thereof is connected with a signal input terminal, a drain thereof is connected with a first level terminal, and a source thereof is connected with a second electrode of the capacitor;
• a second transistor, a gate thereof is connected with a resetting terminal, a drain thereof is connected with the source of the first transistor, and a source thereof is connected with a second level terminal;
• a third transistor, a gate thereof is connected with the source of the first transistor, a drain thereof is connected with a first clock signal terminal, and a source thereof is connected with the output terminal;
• a fourth transistor, a gate thereof is connected with a second clock signal terminal, a drain thereof is connected with the output terminal, and a source thereof is connected with a low level terminal;
• a fifth transistor, a drain thereof is connected with the drain of the second transistor, and a source thereof is connected with the low level terminal;
• a sixth transistor, a gate thereof is connected with a gate of the fifth transistor, a drain thereof is connected with the drain of the fourth transistor, and a source thereof is connected with the source of the fourth transistor;
• a voltage pulling-down control module connected with the second clock signal terminal, the low level terminal, the gate of the fifth transistor, the source of the first transistor, a frame start signal and a third level terminal, wherein in the case that the frame start signal terminal and the third level terminal of the voltage pulling-down module are at high levels simultaneously, the voltage pulling-down control module outputs a high level at the gate of the fifth transistor, and the fifth transistor is in a turn-on state so as to pull down a gate voltage of the third transistor, and the sixth transistor is also in the turn-on state so as to pull down a voltage at the output terminal, wherein, except for a first shift register unit and a last shift register unit of the plurality of shift register units connected in cascade, the output terminal of each of the remaining shift register units is connected with the signal input terminal of the next shift register unit adjacent thereto, the resetting terminal of each of the remaining shift register units is connected with the output terminal of the next shift register unit adjacent thereto, and the frame start signal terminal of each of the remaining shift register units is connected with the respective third level terminal, the third level terminal of the first shift register unit is connected with the second level terminal, the resetting terminal of the first shift register unit is connected with the output terminal of the next shift register unit adjacent thereto, and the third level terminal of the last shift register unit is connected with the first level terminal.