Offset cancelling circuit and method

An offset cancellation circuit, comprising:

• a first switching network having a plurality of inputs and first and second outputs;
• a second switching network having first and second inputs, first and second outputs, and a plurality of connection nodes, the first input of the second switching network coupled to the first output of the first switching network;
• a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to a first connection node of the plurality of connection nodes and the second terminal of the first capacitor coupled to a second connection node of the plurality of connection nodes;
• a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to a third connection node of the plurality of connection nodes and the second terminal of the second capacitor coupled to a fourth connection node of the plurality of connection nodes;
• and
• a first dummy switching element coupled to the first output of the second switching network.

A method for cancelling offset, comprising:

• charging a first capacitor to a first voltage level;
• charging channels of a plurality of dummy switching elements to a first charge level;
• charging a second capacitor to a second voltage level;
• charging the channels of the plurality of dummy switching elements to a second charge level;
• and
• coupling the first and second capacitors in parallel with each other and redistributing the charge from the channels of the plurality of dummy switching elements to the first and second capacitors.

A method for cancelling offset, comprising:

• providing a first switching network having a plurality of inputs and first and second outputs, wherein first, second, third, and fourth inputs of the plurality of inputs are coupled for receiving corresponding Hall element voltages;
• providing a second switching network having first and second inputs and first and second outputs, the first and second inputs of the second switching network coupled to the first and second outputs of the first switching network;
• providing a third switching network having first and second inputs and an output;
• coupling a first capacitor between the first output of the second switching network and the first input of the third switching network;
• coupling a second capacitor between the second output of the second switching network and the second input of the third switching network;
• coupling a plurality of dummy switching elements to the third switching network;
• and
• redistributing charge from the plurality of dummy switching elements to the third switching network.