Semiconductor Drive Circuit and Power Conversion Apparatus Using Same

A power conversion apparatus employing a semiconductor drive circuit, comprising:

• a plurality of arms each of which is formed of an upper arm and a lower arm including a series connection of switching devices using a wide band gap semiconductor;
• and
• gate drive circuits for respectively driving the switching devices of the arms, wherein:
• in each of the arms, the drain terminal of the switching device of the upper arm is connected to the positive terminal of a first power supply, the source terminal of the switching device of the lower arm is connected to the negative terminal of the first power supply, and the source terminal of the switching device of the upper arm is connected with the drain terminal of the switching device of the lower arm;
• a load is connected between the arms' connection points each of which connects the source terminal of the switching device of the upper arm with the drain terminal of the switching device of the lower arm;
• the gate drive circuit provided for each switching device includes an FET circuit and a parallel circuit made of a parallel connection of a first resistor and a first capacitor and having a first terminal connected to the gate terminal of the switching device;
• the source terminal of the FET circuit is connected to a second terminal of the parallel circuit, the gate terminal of the FET circuit is connected to one terminal of a second capacitor, a second resistor is connected between the drain and gate terminals of the FET circuit, and a second power supply is connected between the drain terminal of the FET circuit and the other terminal of the second capacitor;
• the second power supply is a three-level power supply outputting three levels of zero potential, a positive value and a negative value and is an alternating power supply having periods in which its output takes on the zero potential between the positive value and the negative value;
• the second power supply is configured so that the negative value is applied to one of two gate drive circuits for driving the switching devices of the upper and lower arms in periods in which the positive value is applied to the other of the two gate drive circuits;
• and
• the other terminal of the second capacitor connected to the gate terminal of the FET circuit is connected to the source terminal of the switching element.