Airgap interconnect with hood layer and method of formiing

A method for forming a semiconductor device comprising:

• providing a substrate having a dielectric layer with a plurality of interconnects formed therein, wherein each interconnect has a top surface and a side surface;
• forming a hardmask on the dielectric layer and patterning the hardmask to expose the dielectric layer surface between adjacent interconnects;
• etching the dielectric layer between the two adjacent interconnects to form a trench, wherein the etching process exposes at least a portion of the side surface of each adjacent interconnect;
• and
• electrolessly plating a hood layer onto the exposed portion of the top surface and the exposed portion of each side surface.

A method for forming a semiconductor device, comprising:

• providing a substrate having a dielectric layer with a plurality of copper interconnects formed therein, wherein each copper interconnect has a top surface and a side surface, and wherein the side surface is covered by a barrier layer;
• forming a hardmask on the dielectric layer;
• patterning the hardmask to expose a portion of the surface of the dielectric layer between adjacent copper interconnects;
• etching the dielectric layer between the adjacent copper interconnects to form a trench, wherein the etching process etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect;
• electrolessly plating a cobalt hood layer onto an exposed portion of the top surface and the exposed portion of each side surface;
• forming a gap-sealing dielectric layer over the hardmask, the cobalt hood layer and the trench, wherein the gap-sealing dielectric layer seals the trench to form an airgap.