Loading patent…
AssigneeJiangyin Changdian Advanced Packaging Co., Ltd
InventorsLi Zhang, Zhiming Lai, Dong Chen, Jinhui Chen
Estimating the term…
A low-k chip packaging structure comprising chip body I (2-1), a chip electrode (2-2), and a chip surface passivation layer (2-3). Chip body I (2-1) has coated thereon thin film layer I (2-3). Thin film layer I (2-3) has arranged on a rear face thereof a support wafer (2-5). A chip electrode (2-2) is transferred to thin film layer I (2-4) around the exterior of the chip via a rewired metal wiring (2-6). The rewired metal wiring (2-6) has arranged at an end thereof a metal column (2-7). The metal column (2-7) has coated thereon thin film layer II (2-8). The top of the metal column protrudes thin film layer II (2-8). The protruding top of the metal column (2-7) has arranged thereon a metal layer (2-9). The metal layer (2-9) has arranged thereon soldering balls (2-10). The low-k chip packaging structure solves the problem of invalid low-k chip due to concentration of stress during chip packaging process and allows for reduced packaging costs and great product reliability.
A low-k chip packaging structure, comprising a chip body I (2-1), chip electrodes (2-2) and a chip surface passivation layer (2-3), wherein, the chip body (2-1) is wrapped with a film layer I (2-4), the back of the film layer I (2-4) is bonded with a supporting wafer (2-5), the chip electrodes (2-2) are led to the film layer I (2-4) in the peripheral area around the chip via metal redistribution wires (2-6), metal posts (2-7) are arranged at the terminals of the metal redistribution wires (2-6), and the metal posts (2-7) are wrapped with a film layer II (2-8), with the top of the metal posts (2-7) exposed out of the film layer II (2-8);
Dependencies are inferred from the claim text.