Spacer assisted pitch division lithography

A method for fabricating an integrated circuit, comprising:

• providing a variable pitch backbone pattern on a substrate, the pattern having two or more line widths and two or more space widths;
• depositing a conformal layer of spacer material on the pattern and substrate, wherein the conformal layer has a thickness of 1×, and at least one of the space widths of the pattern is 2× or less and is filled with the spacer material;
• and
• removing excess spacer material so as to reveal a top surface of the backbone pattern and to reveal a top surface of the substrate below space widths of the pattern that are greater than 2×, wherein spacer material having a thickness of 1× remains on sidewalls of the pattern, and space widths of the pattern that are 2× or less remain at least partially filled with the spacer material.

A partially-formed integrated circuit, comprising:

• a variable pitch backbone pattern on a substrate, the pattern having two or more line widths and two or more space widths;
• a selectively provisioned conformal layer of spacer material on the pattern and substrate, wherein the conformal layer has a thickness of 1×, and at least one of the space widths of the pattern is 2× or less and is filled with the spacer material;
• and
• wherein excess spacer material has been removed so as to reveal a top surface of the backbone pattern and to reveal a top surface of the substrate below space widths of the pattern that are greater than 2×, wherein spacer material having a thickness of 1× remains on sidewalls of the pattern, and space widths of the pattern that are 2× or less remain at least partially filled with the spacer material.