US 2014/0191338 A1Published application

Semiconductor device and method for manufacturing same

AssigneeRenesas Electronics Corporation

InventorsKoji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Kengo Masuda

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Abstract

In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

Claims10

Dependent claims

A semiconductor device having a static random access memory, comprising:

a storage node including a first storage node and a second storage node storing data;
a pair of bit lines sending/receiving data;
a ground interconnection to which a ground potential is applied;
a first element formation region and a second element formation region, each of which is defined by an element isolation insulation film in a predetermined region of a main surface of a semiconductor substrate;
an access transistor formed in said first element formation region and including a first source-drain region and a second source-drain region that are spaced away from each other and have first conductivity type, said access transistor including an access gate electrode positioned above a region interposed between said first source-drain region and said second source-drain region;
and
a drive transistor formed in said first element formation region and including a third source-drain region and a fourth source-drain region that are spaced away from each other and have the first conductivity type, said drive transistor including a drive gate electrode positioned above a region interposed between said third source-drain region and said fourth source-drain region,
said access transistor including
a first halo region having a first purity concentration and second conductivity type, said first halo region being formed in a region just below said access gate electrode so as to be adjacent to said first source-drain region electrically connected to a predetermined bit line of said pair of bit lines, and
a second halo region having a second impurity concentration and the second conductivity type, said second halo region being formed in the region just below said access gate electrode so as to be adjacent to said second source-drain region electrically connected to said storage node,
said drive transistor including
a third halo region having a third impurity concentration and the second conductivity type, said third halo region being formed in a region just below said drive gate electrode so as to be adjacent to said third source-drain region electrically connected to said storage node, and
a fourth halo region having a fourth impurity concentration and the second conductivity type, said fourth halo region being formed in the region just below said drive gate electrode so as to be adjacent to said fourth source-drain region electrically connected to said ground interconnection,
said second impurity concentration being higher than said first impurity concentration,
said third impurity concentration being higher than said fourth impurity concentration,
said first impurity concentration and said fourth impurity concentration being set to be different impurity concentrations.

13 more elements

A semiconductor device having a static random access memory, comprising:

a storage node including a first storage node and a second storage node storing data;
a first pair of bit lines and a second pair of bit lines both sending/receiving data;
a ground interconnection to which a ground potential is applied;
a first element formation region and a second element formation region, each of which is defined by an element isolation insulation film in a predetermined region of a main surface of a semiconductor substrate;
a first access transistor formed in said first element formation region and including a first source-drain region and a second source-drain region that are spaced away from each other and have first conductivity type, said first access transistor including a first access gate electrode positioned above a region interposed between said first source-drain region and said second source-drain region;
a drive transistor formed in said first element formation region and including a third source-drain region and a fourth source-drain region that are spaced away from each other and have the first conductivity type, said drive transistor including a drive gate electrode positioned above a region interposed between said third source-drain region and said fourth source-drain region;
and
a second access transistor formed in said first element formation region and including a fifth source-drain region and a sixth source-drain region that are spaced away from each other and have the first conductivity type, said second access transistor including a second access gate electrode positioned above a region interposed between said fifth source-drain region and said sixth source-drain region,
said first access transistor including
a first halo region having a first impurity concentration and second conductivity type, said first halo region being formed in a region just below said first access gate electrode so as to be adjacent to said first source-drain region electrically connected to a predetermined bit line of said first pair of bit lines, and
a second halo region having a second impurity concentration and the second conductivity type, said second halo region being formed in the region just below said first access gate electrode so as to be adjacent to said second source-drain region electrically connected to said storage node,
said drive transistor including
a third halo region having a third impurity concentration and the second conductivity type, said third halo region being formed in a region just below said drive gate electrode so as to be adjacent to said third source-drain region electrically connected to said storage node, and
a fourth halo region having a fourth impurity concentration and the second conductivity type, said fourth halo region being formed in the region just below said drive gate electrode so as to be adjacent to said fourth source-drain region electrically connected to said ground interconnection,
said second access transistor including
a fifth halo region having a fifth impurity concentration and the second conductivity type, said fifth halo region being formed in a region just below said second access gate electrode so as to be adjacent to said fifth source-drain region electrically connected to a predetermined bit line of said second pair of bit lines, and
a sixth halo region having a sixth impurity concentration and the second conductivity type, said sixth halo region being formed in the region just below said second access gate electrode so as to be adjacent to said sixth source-drain region electrically connected to said storage node,
said second impurity concentration being higher than said first impurity concentration,
said third impurity concentration being higher than said fourth impurity concentration,
said first impurity concentration and said fourth impurity concentration being set to be different impurity concentrations,
said fifth impurity concentration being set to be lower than said sixth impurity concentration.

18 more elements

A semiconductor device having a static random access memory, comprising:

a storage node including a first storage node and a second storage node storing data;
a first pair of bit lines and a second pair of bit lines both sending/receiving data;
a ground interconnection to which a ground potential is applied;
a first element formation region and a second element formation region, each of which is defined by an element isolation insulation film in a predetermined region of a main surface of a semiconductor substrate;
a first access transistor formed in said first element formation region and including a first source-drain region and a second source-drain region that are spaced away from each other and have first conductivity type, said first access transistor including a first access gate electrode positioned above a region interposed between said first source-drain region and said second source-drain region;
a first drive transistor formed in said first element formation region and including a third source-drain region and a fourth source-drain region that are spaced away from each other and have the first conductivity type, said first drive transistor including a first drive gate electrode positioned above a region interposed between said third source-drain region and said fourth source-drain region;
a second access transistor formed in said first element formation region and including a fifth source-drain region and a sixth source-drain region that are spaced away from each other and have the first conductivity type, said second access transistor including a second access gate electrode positioned above a region interposed between said fifth source-drain region and said sixth source-drain region;
and
a second drive transistor formed in said first element formation region and including a seventh source-drain region and an eighth source-drain region that are spaced away from each other and have the first conductivity type, said second drive transistor including a second drive gate electrode positioned above a region interposed between said seventh source-drain region and said eighth source-drain region,
said first access transistor including
a first halo region having a first impurity concentration and second conductivity type, said first halo region being formed in a region just below said first access gate electrode so as to be adjacent to said first source-drain region electrically connected to a predetermined bit line of said first pair of bit lines, and
a second halo region having a second impurity concentration and the second conductivity type, said second halo region being formed in the region just below said first access gate electrode so as to be adjacent to said second source-drain region electrically connected to said storage node,
said first drive transistor including
a third halo region having a third impurity concentration and the second conductivity type, said third halo region being formed in a region just below said first drive gate electrode so as to be adjacent to said third source-drain region electrically connected to said storage node, and
a fourth halo region having a fourth impurity concentration and the second conductivity type, said fourth halo region being formed in the region just below said first drive gate electrode so as to be adjacent to said fourth source-drain region electrically connected to said ground interconnection,
said second access transistor including
a fifth halo region having a fifth impurity concentration and the second conductivity type, said fifth halo region being formed in a region just below said second access gate electrode so as to be adjacent to said fifth source-drain region electrically connected to a predetermined bit line of said second pair of bit lines, and
a sixth halo region having a sixth impurity concentration and the second conductivity type, said sixth halo region being formed in the region just below said second access gate electrode so as to be adjacent to said sixth source-drain region electrically connected to said storage node,
said second drive transistor including
a seventh halo region having a seventh impurity concentration and the second conductivity type, said seventh halo region being formed in a region just below said second drive gate electrode so as to be adjacent to said seventh source-drain region electrically connected to said storage node, and
an eighth halo region having an eighth impurity concentration and the second conductivity type, said eighth halo region being formed in the region just below said second drive gate electrode so as to be adjacent to said eighth source-drain region electrically connected to said ground interconnection,
said second impurity concentration being higher than said first impurity concentration,
said third impurity concentration being higher than said fourth impurity concentration,
said first impurity concentration and said fourth impurity concentration being set to be different impurity concentrations,
said fifth impurity concentration being lower than said sixth impurity concentration,
said seventh impurity concentration being set to be higher than said eighth impurity concentration.

23 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/236,067Filed 29 Jul 2011
Published: 10 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 10/00
Static random access memory [sram] devices
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…

Family

US 10,032,781 B2Related patent
US 2014/0191338 A1This patent

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