Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array in which are disposed a plurality of memory cells, each including a first conduction type transistor and a second conduction type transistor;
• a plurality of column-side peripheral circuits which are disposed with the same row-direction interval as the memory cells, and which are disposed corresponding to a group of column-direction memory cells disposed in the column direction;
• a first conduction type well region which is formed within the memory cell array, and in which are formed the second conduction type transistors of the plurality of memory cells;
• a second conduction type well region which is formed within the first conduction type well region and is disposed separately in the row direction, and in which are formed the first conduction type transistors of the plurality of memory cells;
• a second conduction type well contact region which is disposed extending in the row direction among the plurality of memory cells, and which is provided in the plurality of second conduction type well regions;
• a first conduction type well contact region which is disposed extending in the column direction among the plurality of memory cells, and provided in the first conduction type well region;
• a column-side peripheral contact region, which is disposed among the plurality of column-side peripheral circuits, and disposed at a position corresponding to the first conduction type well contact region, and moreover provided in the first conduction type well region and the second conduction type well regions;
• a first conduction type back gate voltage line, which connects to the first conduction type well region within the first conduction type well contact region;
• and
• a second conduction type back gate voltage line, which connects to the second conduction type well region within the second conduction type well contact region.