US 2014/0191316 A1 · MOS TRANSISTORS AND FABRICATION METHOD THEREOF

Abstract

A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.

Claims20

Dependent claims

A method for fabricating an MOS transistor, comprising:

providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate;
forming offset sidewall spacers at both sides of the gate structure;
forming lightly doped regions in portions of the semiconductor substrate at both sides of the gate structure and the offset sidewall spacers;
forming a metal silicide region at each of the lightly doped regions;
forming main sidewall spacers on both sides of the off sidewall spacers;
forming heavily doped regions in portions of the semiconductor substrate at both sides of the main sidewall spacers;
and
forming a second metal silicide region in each of the heavily doped regions.

6 more elements

Dependencies are inferred from the claim text.

Mos transistors and fabrication method thereof

Life of this patent

Mos transistors and fabrication method thereof

Life of this patent

Abstract

Claims20