Integrated Switch Devices

A multiple Field Effect Transistor (FET) device comprising:

• a compound semiconductor layer;
• a sync FET;
• a control FET including a plurality of first control ohmic metal fingers and second control ohmic metal fingers;
• and
• an e-mode FET configured as a normally off component to protect the control FET upon power up of the device, the control FET, sync FET and e-mode FET fabricated on the compound semiconductor layer as a monolithic device.

A multiple Field Effect Transistor (FET) device comprising:

• a compound semiconductor layer;
• a sync and control FET fabricated on the compound semiconductor layer, the sync FET including a first and second sync ohmic metal finger;
• and
• a sense area fabricated on the compound semiconductor layer, the sense area comprising:
• a first sense ohmic metal finger parallel to and aligned with the first sync ohmic metal finger;
• a second sense ohmic metal finger contiguous with the second sync ohmic metal finger;
• a non-conductive region disposed between the first sense ohmic metal finger and the first sync ohmic metal finger;
• and
• a continuous sync gate finger disposed adjacent the first and second sense ohmic metal finger and between the first and second sync ohmic metal finger.

A dual Field Effect Transistor (FET) device comprising:

• a compound semiconductor layer;
• a control FET fabricated on the compound semiconductor layer, the control FET including a source region, a drain region and a gate region, the control FET further comprising:
• an ohmic metal control source finger and an ohmic metal control drain finger disposed on a surface of the compound semiconductor layer in electrical contact with the source region and drain region, respectively,
• a control gate finger between the control source finger and the control drain finger, and
• a first and second control gate pad at opposite ends of the control gate finger and in electrical contact with the control gate finger;
• a sync FET fabricated on the compound semiconductor layer with the control FET as a monolithic device, the sync FET including a source region, a drain region and a gate region, the sync FET further comprising:
• an ohmic metal sync source finger and an ohmic metal sync drain finger disposed on the surface of the compound semiconductor layer in electrical contact with the source region and drain region, respectively,
• a sync gate finger between the sync source finger and the sync drain finger, and
• a first and second sync gate pad at opposite ends of the sync gate finger and in electrical contact with the sync gate finger, the first control gate pad and the first sync gate pad disposed between the control drain finger and the sync source finger;
• an electrical connection between the control source finger and the sync drain finger;
• and
• a sense region comprising:
• an isolated portion of the sync finger;
• a non-conductive region of the sync gate finger configured to electrically isolate the isolated portion of the sync finger from the rest of the sync finger;
• and
• a portion of the sync drain finger adjacent the isolated portion of the sync gate finger.