Transistor and fabrication method
AssigneeSemiconductor Manufacturing International (Shanghai) Corporation
InventorsYOUFENG HE, YONGGEN HE
Life of this patent
Estimating the term…
Abstract
Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate.
Claims20
A method of forming a transistor, comprising:
- forming a gate structure on a semiconductor substrate, the gate structure including a gate dielectric layer on the semiconductor substrate and a gate on the gate dielectric layer;
- forming a first sidewall on each sidewall of the gate structure, wherein the first sidewall is made of a doped material;
- forming a second sidewall on the first sidewall, wherein the second sidewall is formed of a material having an etch rate greater than the first sidewall;
- forming a source and a drain in the semiconductor substrate on both sides of the gate structure;
- forming a metal silicide layer on the semiconductor substrate associated with each of the source and the drain, such that the second sidewall on the semiconductor substrate is between the metal silicide layer and the first silicide layer;
- after forming the metal silicide layer, removing the second sidewall to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer;
- and
- forming a stress layer on the surface portion of the semiconductor substrate exposed between the metal silicide layer and the first silicide layer, on the metal silicide layer, on the first sidewall, and on the gate.
A transistor comprising:
- a gate structure disposed on a semiconductor substrate, the gate structure including a gate dielectric layer on the semiconductor substrate and a gate on the gate dielectric layer;
- a first sidewall disposed on each sidewall of the gate structure, wherein the first sidewall is made of a doped material;
- a source and a drain in the semiconductor substrate on both sides of the gate structure;
- a metal silicide layer disposed on the semiconductor substrate associated with each of the source and the drain, wherein a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer is exposed;
- and
- a stress layer disposed on the surface portion of the semiconductor substrate exposed between the metal silicide layer and the first silicide layer, on the metal silicide layer, on the first sidewall, and on the gate.
Dependencies are inferred from the claim text.