US 2014/0191287 A1 · COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE

Abstract

A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

Claims11

Dependent claims

A semiconductor device comprising:

a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension IIII-V semiconductor layer has a compressive strain present therein;
a gate structure present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain;
and
a source region and a drain region on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/027,563Filed 16 Sep 2013

Priority

8 Jan 2013

Published

10 Jul 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 30/47
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having two-dimensional [2D] charge…
H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10D 30/4755
Having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs: having wide bandgap…
H10D 30/751
Insulated-gate field-effect transistors [IGFET]: having composition variations in the channel regions

Compressive strained iii-v complementary metal oxide semiconductor (cmos) device

Life of this patent

Compressive strained iii-v complementary metal oxide semiconductor (cmos) device

Life of this patent

Abstract

Claims11