High voltage semiconductor device

A high voltage semiconductor device, comprising:

• a second conductivity type semiconductor region provided on a first conductivity type semiconductor substrate;
• a logic circuit provided in the surface layer of the semiconductor region;
• an insulated gate field effect transistor having a second conductivity type source region provided on the outer peripheral side of the semiconductor region, a gate electrode provided on the semiconductor region via an insulating film, and a second conductivity type drain region provided in the surface layer of the semiconductor region so as to be spaced a predetermined distance from the outer peripheral edge of the semiconductor region;
• a second conductivity type pick-up region provided in the surface layer of the semiconductor region, away from the drain region, so as to be spaced the predetermined distance from the outer peripheral edge of the semiconductor region;
• a trench, reaching the semiconductor substrate from the surface of the semiconductor region, provided away from the drain region, second conductivity type pick-up region, and logic circuit, between the logic circuit and a region from the drain region to a portion of the semiconductor region extending to one drain region side portion of the second conductivity type pick-up region via a portion of the semiconductor region sandwiched between the drain region and second conductivity type pick-up region;
• an insulating body buried in the trench;
• and
• a load resistance formed of a portion of the semiconductor region sandwiched between the drain region and second conductivity type pick-up region.

A high voltage semiconductor device which drives a switching element of which the high potential side terminal is connected to a high voltage power source and the low potential side terminal is connected to an OUT terminal which can take the potential between the high potential and ground potential of the high voltage power source, the device comprising:

• a second conductivity type semiconductor region provided on a first conductivity type semiconductor substrate;
• a logic circuit provided in the surface layer of the semiconductor region using as a power source a low potential power source with the OUT terminal as a reference;
• an insulated gate field effect transistor having a first conductivity type base region annularly provided on the outer peripheral side of the semiconductor region, a second conductivity type source region provided inside the base region, a gate electrode provided on the semiconductor region via an insulating film, and a second conductivity type drain region provided in the surface layer of the semiconductor region so as to be spaced a predetermined distance from the base region;
• a second conductivity type pick-up region provided in the surface layer of the semiconductor region, away from the drain region, so as to be spaced a predetermined distance from the base region, and connected on the high potential side of the low potential power source with the OUT terminal as the reference;
• a first conductivity type pick-up region provided inside the base region and connected to the ground of a low potential power source with the ground as a reference;
• and
• a region wherein the first conductivity type pick-up region is not formed, and parasitic resistance components Rp are provided, in a region of the source region close in the channel width direction of the insulated gate field effect transistor.