US 2014/0191256 A1Published application

Thin film trannsistor array panel and manufacturing method thereof

AssigneeSamsung Display Co., Ltd.

InventorsJeong Min PARK, Ji-Hyun KIM, Jung-Soo LEE, Sung Kyun PARK

Life of this patent

Estimating the term…

Loading patent…

Abstract

Instead of forming contact holes the same way in both the non-image forming peripheral area (PA) and the image forming display area of a thin film transistor array panel, contact holes in the DA are formed to be substantially smaller than those in the PA for thereby improving an aperture ratio of the corresponding display device. In an exemplary embodiment, an inorganic gate insulating layer is not etched in the DA and only an inorganic first passivation layer among inorganic insulating layers positioned in the DA is etched to allow communication between the drain electrode and the corresponding field generating electrode. On the other hand, in the peripheral area, plural inorganic insulating layers such as the gate insulating laver, the first passivation laver, and the second passivation layer positioned on the gate wire and the data wire are simultaneously etched to form second contact holes and third contact holes exposing respective gate pads and data pads.

Claims20

Dependent claims

A thin film transistor array panel for use in a display device and comprising:

a substrate having a display area through which image forming light rays of the display device will pass and a peripheral area disposed near the display area and through which image forming light rays of the display device will not pass;
a gate line positioned in the display area of the substrate;
a gate pads connected to the gate line and positioned in the peripheral area of the substrate;
a gate insulating layer positioned on the gate line and the gate pad;
a data line and a drain electrode positioned in the display area of the substrate;
a data pad connected to the data line and positioned in the peripheral area of the substrate and on the gate insulating layer;
a first passivation layer having a first contact hole defined therethrough for exposing a portion of the drain electrode;
a first field generating electrode connected to the drain electrode through the first contact hole of the first passivation layer;
a second passivation layer positioned on the first field generating electrode;
and
a second field generating electrode positioned on the second passivation layer,
wherein the first field generating electrode include a portion positioned in the first contact hole covered by the second passivation layer,
wherein the gate insulating layer, the first passivation layer, and the second passivation layer have second contact hole extending therethrough and positioned in the peripheral area for exposing the gate pad, and
wherein the first passivation layer and the second passivation layer have a third contact hole extending therethrough and positioned in the peripheral area for exposing the data pad.

11 more elements

A method of manufacturing a thin film transistor array panel for use in a display device, the method comprising:

providing a substrate having a peripheral area and a display area, where the display area is one through which image forming light rays of the display device will pass and the peripheral area is one through which image forming light rays of the display device will not pass;
forming a gate line in the display area of the substrate and a gate pad in the peripheral area of the substrate;
forming a gate insulating layer on the gate line and the gate pad;
forming a data line and a drain electrode in the display area of the substrate and a data pad in the peripheral area of the substrate;
depositing a first passivation layer in the peripheral area and in the display area of the substrate;
etching the first passivation layer to form a first contact hole exposing a portion of the drain electrode;
forming a first field generating electrode connected to the drain electrode through the first contact hole;
depositing a second passivation layer on the first field generating electrode;
etching the gate insulating layer, the first passivation layer, and the second passivation layer positioned in the peripheral area to form a second contact hole exposing the gate pad, and etching the first passivation layer and the second passivation layer to form a third contact hole exposing the data pad;
and
forming a second field generating electrode on the second passivation layer;
wherein the first contact hole is narrower than either of the second and third contact holes.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/090,487Filed 26 Nov 2013
Priority: KR 10-2013-000298210 Jan 2013
Published: 10 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G02F 1/13458
Conductors connecting electrodes to cell terminals: terminal pads
G02F 1/136227
Active matrix addressed cells: through-hole connection of the pixel electrode to the active element through an insulation layer
G02F 1/1368
Active matrix addressed cells: in which the switching element is a three-electrode device

Family

US 9,123,873 B2Related patent
US 2014/0191256 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key