Method and system for a gallium nitride vertical transistor

A method of fabricating a vertical JFET, the method comprising:

• providing a III-nitride epitaxial structure including:
• a III-nitride substrate;
• and
• a plurality of epitaxial layers coupled to the III-nitride substrate;
• removing a portion of the plurality of epitaxial layers to form a set of recesses extending a predetermined distance into the plurality of epitaxial layers, wherein the set of recesses are disposed between remaining portions of the plurality of epitaxial layers;
• regrowing a plurality of regrown epitaxial layers coupled to at least a portion of one of the plurality of epitaxial layers and the remaining portions of the plurality of epitaxial layers, wherein one of the plurality of regrown epitaxial layers is electrically coupled to one of the plurality of epitaxial layers;
• removing a portion of the plurality of regrown epitaxial layers to expose a portion of the one of the plurality of epitaxial layers;
• forming a source contact electrically coupled to the one of the plurality of epitaxial layers;
• forming a gate contact electrically coupled to another of the plurality of epitaxial layers;
• and
• forming a drain contact electrically coupled to the III-nitride substrate.