Semiconductor device

A semiconductor device comprising:

• a gate electrode layer;
• a gate insulating layer adjacent to the gate electrode layer;
• and
• an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,
• wherein a carrier concentration of the oxide semiconductor layer is less than 1×1012/cm3,
• wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less,
• wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm,
• wherein a thickness of the gate insulating layer is 20 nm to 50 nm, and
• wherein the oxide semiconductor layer comprises indium and zinc.

A semiconductor device comprising a transistor, the transistor comprising:

• a gate electrode layer;
• a gate insulating layer adjacent to the gate electrode layer;
• and
• an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,
• wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less,
• wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm,
• wherein a thickness of the gate insulating layer is 20 nm to 50 nm,
• wherein the oxide semiconductor layer includes a region in which a concentration of hydrogen is 5×1019/cm3 or less,
• wherein an off current per micrometer in a channel width is 100 aA/μm or less when a drain voltage of 1 V to 10 V is applied, and
• wherein the oxide semiconductor layer comprises indium and zinc.

A semiconductor device comprising:

• an oxide semiconductor layer;
• a source electrode layer and a drain electrode layer over the oxide semiconductor layer;
• a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
• and
• a gate electrode layer over the gate insulating layer;
• wherein the gate electrode layer overlaps the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,
• wherein a carrier concentration of the oxide semiconductor layer is less than 1×1012/cm3,
• wherein a length of a channel formed in the oxide semiconductor layer is 3.0 μm or less,
• wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm,
• wherein a thickness of the gate insulating layer is 20 nm to 50 nm, and
• wherein the oxide semiconductor layer comprises indium and zinc.