Vertical bipolar transistor
AssigneeSTMicroelectronics (Rousset) SAS
InventorsPhilippe Boivin, Francesco La Rosa, Julien Delalleau
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Abstract
The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
Claims13
An integrated circuit, comprising:
- a transistor having:
- first and second conduction terminals;
- a control terminal;
- a stack of a first dielectric layer, a conductive layer, and a second dielectric layer,
- the first conduction terminal of the transistor including a first semiconductor region of a first conductivity type formed in the first dielectric layer,
- the control terminal of the transistor including a second semiconductor region of a second conductivity type formed in the conductive layer, and
- the second conduction terminal of the transistor including a third semiconductor region of the first conductivity type formed in the second dielectric layer.
A memory cell, comprising:
- a data storage element;
- a transistor coupled to the data storage element, the transistor having:
- a first dielectric layer;
- a conductive layer;
- a second dielectric layer;
- a first conduction terminal including a first semiconductor region of a first conductivity type formed in the first dielectric layer;
- a control terminal including a second semiconductor region of a second conductivity type formed in the conductive layer;
- and
- a second conduction terminal including a third semiconductor region of the first conductivity type formed in the second dielectric layer.
A device, comprising:
- an array of memory cells the memory cells being arranged in at least one row, each memory cell including:
- a data storage element;
- a transistor coupled to the data storage element, the transistor having:
- a first dielectric layer;
- a conductive layer;
- a second dielectric layer;
- a first conduction terminal including a first semiconductor region of a first conductivity type formed in the first dielectric layer;
- a control terminal including a second semiconductor region of a second conductivity type formed in the conductive layer;
- and
- a second conduction terminal including a third semiconductor region of the first conductivity type formed in the second dielectric layer;
- the conductive layer extends between and is shared with each transistor in a row and is coupled to the control terminals of all memory cells of the row.
A method, comprising:
- forming a transistor that includes first and second conduction terminals and a control terminal, the forming of the transistor including:
- forming a stack of a first dielectric layer, a conductive layer, and a second dielectric layer;
- forming the first conduction terminal as a first semiconductor region of a first conductivity type in the first dielectric layer;
- forming the control terminal as a second semiconductor region of a second conductivity type in the conductive layer;
- and
- forming the second conduction terminal as a third semiconductor region of the first conductivity type in the second dielectric layer.
Dependencies are inferred from the claim text.