US 2014/0181463 A1Published application

Dynamic Address Translation with Translation Table Entry Format Control for Identifying Format of the Translation Table Entry

AssigneeInternational Business Machines Corporation

InventorsDan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb

Life of this patent

Estimating the term…

Loading patent…

Abstract

An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

Claims20

Dependent claims

A computer program product for translation of a virtual address into a translated address of a desired block in main storage in a computer system of a machine architecture, the computer program product comprising:

a computer readable storage medium readable by a processor of said computer system, said computer readable medium storing instructions for performing:
based on an initial origin address of a translation table of a hierarchy of translation tables comprising a segment table, obtaining, by the processor, a segment table entry from said segment table, said segment table entry configured to include a format control field for determining a format of the segment table entry;
and
based on said format control field being enabled, performing, by the processor, a)-c):
a) obtaining from said segment table entry, by the processor, a segment-frame absolute address of a large block of main storage;
b) combining, by the processor, said segment-frame absolute address with a page index portion of said virtual address and a byte index portion of said virtual address to form the translated address of the desired block of main storage within said large block of main storage, wherein the formed translated address consists of said segment-frame absolute address, said page index portion of said virtual address, and said byte index portion of said virtual address, wherein said desired block of main storage consists of one or more bytes of data;
and
c) accessing said desired block of main storage addressed by said translated virtual address.

5 more elements

A computer system for translation of a virtual address into a translated address of a desired block of data in main storage in a computer system of a machine architecture, the system comprising:

a computer memory for storing machine instructions and a hierarchy of translation tables used for dynamic address translation of a virtual address into a real address or absolute address of a desired block of data in said main storage, said real address being subject to a prefixing operation;
and
a processor in communication with said computer memory, said processor for accessing said hierarchy of translation tables stored in said memory, said processor performing a method comprising:
based on an initial origin address of a translation table of a hierarchy of translation tables comprising a segment table, obtaining, by the processor, a segment table entry from said segment table, said segment table entry configured to include a format control field for determining a format of the segment table entry;
and
based on said format control field being enabled, performing, by the processor, a)-c):
a) obtaining from said segment table entry, by the processor, a segment-frame absolute address of a large block of main storage;
b) combining, by the processor, said segment-frame absolute address with a page index portion of said virtual address and a byte index portion of said virtual address to form the translated address of the desired block of main storage within said large block of main storage, wherein the formed translated address consists of said segment-frame absolute address, said page index portion of said virtual address, and said byte index portion of said virtual address, wherein said desired block of main storage consists of one or more bytes of data;
and
c) accessing said desired block of main storage addressed by said translated virtual address.

7 more elements

A computer implemented method for translation in a computer system of a machine architecture having a CPU, a memory, and a hierarchy of translation tables used for translation of a virtual address into a translated address of a block of data in main storage, the method comprising:

based on an initial origin address of a translation table of a hierarchy of translation tables comprising a segment table, obtaining, by the processor, a segment table entry from said segment table, said segment table entry configured to include a format control field for determining a format of the segment table entry;
and
based on an initial origin address of a translation table of a hierarchy of translation tables comprising a segment table, obtaining, by the processor, a segment table entry from said segment table, said segment table entry configured to include a format control field for determining a format of the segment table entry;
and
based on said format control field being enabled, performing, by the processor, a)-c):
a) obtaining from said segment table entry, by the processor, a segment-frame absolute address of a large block of main storage;
b) combining, by the processor, said segment-frame absolute address with a page index portion of said virtual address and a byte index portion of said virtual address to form the translated address of the desired block of main storage within said large block of main storage, wherein the formed translated address consists of said segment-frame absolute address, said page index portion of said virtual address, and said byte index portion of said virtual address, wherein said desired block of main storage consists of one or more bytes of data;
and
c) accessing said desired block of main storage addressed by said translated virtual address.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/133,796Filed 19 Dec 2013
Priority: 11 Jan 2008
Published: 26 Jun 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 12/1009
Address translation: using page tables, e.g. page table structures
G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F
Computing and data processing

Family

Application11/972,697Continuation · filed 11 Jan 2008
Application13/336,106Continuation · filed 23 Dec 2011
Application14/133,796Continuation
US 2009/0182972 A1Published application
US 2012/0137106 A1Published application
US 8,103,851 B2Related patent
US 8,621,180 B2Related patent
US 9,244,856 B2Related patent
US 2014/0181463 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key