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US 2014/0181351 A1Published application
Intelligent interrupt distributor
AssigneeNXP B.V.
InventorsHamed Fatemi, Ajay Kapoor, Jose de Jesus Pineda de Gyvez, Juan Diego Echeverri Escobar
Life of this patent
Estimating the term…
Abstract
An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.
Claims11
A multiprocessor system comprising:
- a first processor;
- a second processor coupled to the first processor by a first bus;
- a second bus coupled to the first bus;
- a clock gating unit directly coupled to the first processor and the second processor;
- a first and second peripheral device coupled to the second bus;
- and
- an intelligent interrupt distributor coupled to the first bus and directly coupled to the first and second processor by an interrupt bus and directly coupled to the first and second peripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating unit such that an interrupt received on the first or the second peripheral interrupt line is distributed via the interrupt line to one of the first and the second processors which is in an idle state.
4 more elements
A method for making a multiprocessor system comprising:
- providing a first processor;
- providing a second processor coupled to the first processor by a first bus;
- providing a second bus coupled to the first bus;
- providing a clock gating unit directly coupled to the first processor and the second processor;
- providing a first and second peripheral device coupled to the second bus;
- and
- an intelligent interrupt distributor coupled to the first bus and directly coupled to the first and second processor by an interrupt bus and directly coupled to the first and second peripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating unit such that an interrupt received on the first or the second peripheral interrupt line is distributed via the interrupt line to one of the first and the second processors which is in an idle state.
4 more elements
Dependencies are inferred from the claim text.