Method, apparatus, system for single-path floating-point rounding flow that supports generation of normals/denormals and associated status flags

A computer-implemented method, comprising:

• generating, by a floating point unit (FPU) of a processing device, a plurality of status flags for a rounded value of a finite nonzero number, wherein the plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number, wherein the plurality of status flags comprises an overflow flag and an underflow flag;
• determining, by the FPU, whether the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted;
• upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, calculating, by the FPU, the rounded value of the finite nonzero number based on an overflow rounding;
• and
• upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is not asserted, calculating, by the FPU, the rounded value of the finite nonzero number based on a blended reduced precision rounding.

A non-transitory machine-readable storage medium including data that, when accessed by a machine, cause the machine to perform operations comprising:

• generating, by a processing device of the machine, a plurality of status flags for a rounded value of a finite nonzero number, wherein the plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number, wherein the plurality of status flags comprises an overflow flag and an underflow flag;
• determining, by the processing device, whether the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted;
• upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, calculating, by the processing device, the rounded value of the finite nonzero number based on an overflow rounding;
• and
• upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is not asserted, calculating, by the processing device, the rounded value of the finite nonzero number based on a blended reduced precision rounding.

A processing device comprising:

• a plurality of registers;
• a main processing unit;
• and
• a floating point unit (FPU) communicably coupled to the main processing unit, the FPU to:
• generate a plurality of status flags for a rounded value of a finite nonzero number, wherein the plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number, wherein the plurality of status flags comprises an overflow flag and an underflow flag;
• determine whether the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted;
• upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, calculate the rounded value of the finite nonzero number based on an overflow rounding;
• and
• upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is not asserted, calculate the rounded value of the finite nonzero number based on a blended reduced precision rounding.