US 2014/0175520 A1 · METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME

Abstract

The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance RB of the prior art products. The metal silicide self-aligned SiGe heterojunction bipolar transistor of the present invention mainly comprises an Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region composed of a liner silicon oxide layer and a silicon nitride inner sidewall, a monocrystalline emitter region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode. The base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region. The present invention discloses a method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is used to form the aforesaid bipolar transistor. The metal silicide self-aligned SiGe heterojunction bipolar transistor and the method of forming the same of the present invention can reduce the base resistance RB, and feature a simple process and a low cost.

Claims31

Dependent claims

A metal silicide self-aligned SiGe heterojunction bipolar transistor, comprising a Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region, a monocrystalline emitter region beneath an emitter window enclosed by the emitter-base spacer dielectric region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode, wherein the emitter-base spacer dielectric region is composed of a liner silicon oxide layer and a silicon nitride inner sidewall, and the base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region;

and
wherein the base region comprises a monocrystalline base region, a polycrystalline base region and a polysilicon elevated extrinsic base region, the monocrystalline base region and the polycrystalline base region are located above the Si collector region and the local dielectric region, the polysilicon emitter region and the emitter-base spacer dielectric region are located above the monocrystalline base region, the base-region low-resistance metal silicide layer is located on surfaces of the polycrystalline base region and a portion of the monocrystalline base region, and the polysilicon elevated extrinsic base region is located above the base-region low-resistance metal silicide layer.

A method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, comprising at least the following steps:

6.1 forming a Si epitaxial layer of a first conduction type and forming a local dielectric region in the resulting Si epitaxial layer, wherein a portion of the Si epitaxial layer in which the local dielectric region is not formed forms a Si collector region;
6.2 forming a base region of a second conduction type on the resulting structure of the step 6.1, forming a monocrystalline base region on top of the Si collector region, and forming a polycrystalline base region on top of the local dielectric region, wherein the base region is a composite layer consisting of Si and SiGe;
6.3 depositing or sputtering a first metal layer;
6.4 depositing a first silicon oxide layer;
6.5 selectively removing middle portions of the first silicon oxide layer and the first metal layer in sequence to form a first window which exposes the middle portion of the surface of the monocrystalline base region;
6.6 depositing a second silicon oxide layer;
6.7 depositing a silicon nitride layer and then forming a silicon nitride inner sidewall at the inner edge of the first window through an anisotropic etching process;
6.8 removing portions of the second silicon oxide layer which are not covered by the silicon nitride inner sidewall to form an emitter-base spacer dielectric region composed of a liner silicon oxide layer and the silicon nitride inner sidewall, opening an emitter window enclosed by the emitter-base spacer dielectric region to expose the middle portion of the surface of the monocrystalline base region;
6.9 depositing a polysilicon layer and heavily doping the polysilicon layer into a polysilicon layer of the first conduction type;
6.10 forming a protection layer on the polysilicon layer and then etching off portions of the polysilicon layer and the first silicon oxide layer which are not masked by the protection layer to form a heavily doped polysilicon emitter region of the first conduction type;
6.11 implanting ions of the second conduction type into the resulting structure of the step 6.10 to form a heavily doped monocrystalline base region and a heavily doped polycrystalline base region of the second conduction type by using the protection layer as a mask, and then removing the protection layer;
6.12 enabling the first metal layer to make a silicification reaction with the heavily doped polycrystalline base region, the heavily doped monocrystalline base region and a portion of the monocrystalline base region, which are in contact with the first metal layer, respectively, to obtain a base-region low-resistance metal silicide layer;
and diffusing the impurities in the heavily doped polysilicon emitter region of the first conduction type formed in the step 6.10 outwards and downwards via the emitter window to form a heavily doped monocrystalline emitter region of the first conduction type;
and
6.13 depositing a contact hole dielectric layer, forming contact holes, and leading out an emitter metal electrode and a base metal electrode.

12 more elements

A method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, comprising at least the following steps:

8.1 forming a Si epitaxial layer of a first conduction type and forming a local dielectric region in the resulting Si epitaxial layer, wherein a portion of the Si epitaxial layer in which the local dielectric region is not formed forms a Si collector region;
8.2 forming a base region of a second conduction type on the resulting structure of the step 8.1, forming a monocrystalline base region on top of the Si collector region, and forming a polycrystalline base region on top of the local dielectric region, wherein the base region is a composite layer consisting of Si and SiGe;
8.3 depositing or sputtering a first metal layer;
8.4 depositing a first polysilicon layer to form a heavily doped first polysilicon layer of the second conduction type, and depositing a first silicon oxide layer on the first polysilicon layer;
8.5 selectively removing middle portions of the first silicon oxide layer, the first polysilicon layer and the first metal layer in sequence to form a first window which exposes the middle portion of the surface of the monocrystalline base region, with remaining portions of the first polysilicon layer forming a polysilicon elevated extrinsic base region;
8.6 depositing a second silicon oxide layer;
8.7 depositing a silicon nitride layer and then forming a silicon nitride inner sidewall at the inner edge of the first window through an anisotropic etching process;
8.8 removing portions of the second silicon oxide layer which are not covered by the silicon nitride inner sidewall to form an emitter-base spacer dielectric region composed of a liner silicon oxide layer and the silicon nitride inner sidewall, and opening an emitter window enclosed by the emitter-base spacer dielectric region to expose the middle portion of the surface of the monocrystalline base region;
8.9 depositing a second polysilicon layer and heavily doping the second polysilicon layer into a polysilicon layer of the first conduction type;
8.10 etching off portions of the second polysilicon layer and portions of the first silicon oxide layer to form a heavily doped polysilicon emitter region of the first conduction type;
8.11 enabling the metal layer to make a silicification reaction with the polycrystalline base region, a portion of the monocrystalline base region and the polysilicon elevated extrinsic base region, which are in contact with the metal layer, respectively, to obtain a base-region low-resistance metal silicide layer;
and diffusing the impurities in the heavily doped polysilicon emitter region of the first conduction type formed in the step 8.10 outwards and downwards via the emitter window to form a heavily doped monocrystalline emitter region of the first conduction type;
and
8.12 depositing a contact hole dielectric layer, forming contact holes, and leading out an emitter metal electrode and a base metal electrode.

11 more elements

Dependencies are inferred from the claim text.

METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME

Life of this patent

METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME

Life of this patent

Abstract

Claims31