Methods and apparatus for interleaving priorities of a plurality of virtual processors

An apparatus for interleaving priorities of a plurality of virtual processors, the apparatus comprising:

• a hypervisor;
• and
• at least one physical processor operatively coupled to the hypervisor;
• wherein the hypervisor is structured to:
• assign a first maximum priority to a first virtual processor;
• assign a second maximum priority to a second virtual processor, wherein the second maximum priority is lower than the first maximum priority;
• schedule the first virtual processor to execute based on a first current priority associated with the first virtual processor being equal to the first maximum priority;
• receive an indication from the first virtual processor that the first current priority associated with the first virtual processor may be temporarily reduced;
• lower the first current priority associated with the first virtual processor to a temporary priority level, wherein the temporary priority level is lower than the second maximum priority;
• schedule the second virtual processor to execute based on a second current priority associated with the second virtual processor being equal to the second maximum priority;
• receive an interrupt associated with the first virtual processor;
• raise the first current priority associated with the first virtual processor to the first maximum priority in response to the interrupt;
• and
• schedule the first virtual processor to execute again based on the first current priority associated with the first virtual processor being equal to the first maximum priority.

A computer readable memory storing instructions structured to cause an electronic device to:

• assign a first maximum priority to a first virtual processor;
• assign a second maximum priority to a second virtual processor, wherein the second maximum priority is lower than the first maximum priority;
• schedule the first virtual processor to execute based on a first current priority associated with the first virtual processor being equal to the first maximum priority;
• receive an indication from the first virtual processor that the first current priority associated with the first virtual processor may be temporarily reduced;
• lower the first current priority associated with the first virtual processor to a temporary priority level, wherein the temporary priority level is lower than the second maximum priority;
• schedule the second virtual processor to execute based on a second current priority associated with the second virtual processor being equal to the second maximum priority;
• receive an interrupt associated with the first virtual processor;
• raise the first current priority associated with the first virtual processor to the first maximum priority in response to the interrupt;
• and
• schedule the first virtual processor to execute again based on the first current priority associated with the first virtual processor being equal to the first maximum priority.