Enhanced serialization mechanism

A network device having a symmetric multiprocessing architecture, the network device comprising:

• a plurality of CPU cores;
• a network interface to receive one or more data packets;
• and
• a memory whose access is shared by the dedicated CPU core and the plurality of CPU cores;
• wherein the plurality of CPU cores are to:
• receive a plurality of packets from a plurality of transport layer flows corresponding to a security association;
• designate one processor of a plurality of processors to be associated with the security association;
• assign a sequence number to each packet;
• and
• transmit the plurality of packets from the plurality of transport layer flows such that packets within the same transport layer flow are transmitted in order of their sequence numbers.

A non-transitory computer-readable storage medium storing embedded instructions for a plurality of operations that are executed by one or more mechanisms implemented within a network device having a symmetric multiprocessing architecture, the plurality of operations comprising:

• receiving a plurality of packets from a plurality of transport layer flows corresponding to a security association;
• designating one processor of a plurality of processors to be associated with the security association;
• assigning a sequence number to each packet;
• and
• transmitting the plurality of packets from the plurality of transport layer flows such that packets within the same transport layer flow are transmitted in order of their sequence numbers.