Dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof

A dynamic allocation method with load balancing, comprising steps of:

• detecting instruction execution loads of a plurality of microprocessors in past predefined time interval by a work control logic unit;
• said work control logic unit calculating an actual amount of dynamically reconfigurable processors to be assigned to each processor type, and subtracts an amount of already-assigned said dynamically reconfigurable processors from a total amount of said dynamically reconfigurable processors to obtain a further amount of said dynamically reconfigurable processors to be reconfigured and assigned to that processor type, and said total amount of said dynamically reconfigurable processors includes an amount of said dynamically reconfigurable processors at present and said dynamically reconfigurable processors calculated by said work control logic unit and required at next stage;
• setting reconfiguration control signals which transform said dynamic reconfigurable heterogeneous processors into a desired processor type;
• gathering an amount of said dynamically reconfigurable processors to be reconfigured and assigned from a free dynamically reconfigurable processor pool and/or excessive dynamically reconfigurable processors from a lightly loaded type side after they finish their current computation, and generating a ready signal after available said dynamically reconfigurable processors of such amount are ready for their new assignment;
• and
• enabling said reconfiguration control signal using said ready signal such that said available said dynamic reconfigurable processors are properly reconfigured, and rerouting data links in interconnection and routing path according to a updated dynamic reconfigurable processor assignment;
• wherein a method of designing a circuit of said dynamic reconfigurable heterogeneous processor further comprising steps of:
• performing a plurality of hardware requirement analyses using operation requirement trees for basic operations of said microprocessors, wherein each said operation requirement tree comprises a plurality of operation nodes showing an operation required;
• choosing common said operation nodes of said operation requirement trees to establish a plurality of block-selection trees;
• choosing sharable said operation nodes of said block-selection trees and adding a multiplexer operation node at each sharable said operation node, respectively;
• and
• searching all said block-selection trees and choosing said operation nodes and associated said multiplexer operation nodes of said block-selection trees that fulfill all necessary reconfiguration requirements of said dynamic reconfigurable heterogeneous processor.