US 2014/0157223 A1 · CIRCUIT AND LAYOUT DESIGN METHODS AND LOGIC CELLS FOR SOFT ERROR HARD INTEGRATED CIRCUITS

Abstract

In various embodiments, an integrated circuit layout is disclosed. In one embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.

Claims21

Dependent claims

An integrated circuit comprising:

a first contact area from a first logic cell;
and
a second contact area from a second logic cell comprising a non-zero, non-opposing effect with respect to the first contact area, wherein the first contact area and the second contact area comprise a first distance, wherein when the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.

An integrated circuit cell comprising:

a first p-type MOSFET comprising a source coupled to a power net, a drain, and a gate coupled to an input;
a second p-type MOSFET comprising a source coupled to the drain of the first p-type MOSFET, a drain coupled to an inverse output, and a gate;
a third p-type MOSFET comprising a source coupled to the power net, a drain, and a gate coupled to an inverse input;
a fourth p-type MOSFET comprising a source coupled to the drain of the third p-type MOSFET, a drain coupled to an output, and a gate;
a first n-type MOSFET comprising a source coupled to a ground net, a drain, and a gate coupled to the input;
a second n-type MOSFET comprising a source coupled to the drain of the first n-type MOSFET, a drain coupled to the inverse output, and a gate;
a third n-type MOSFET comprising a source coupled to the ground net, a drain, and a gate coupled to the inverse input;
and
a fourth n-type MOSFET comprising a source coupled to the drain of the third n-type MOSFET, a drain coupled to the output, and a gate.

6 more elements

An integrated circuit comprising:

a first p-type MOSFET comprising a source coupled to a power net of a circuit, a drain coupled to the output, and a gate coupled to the first input;
a second p-type MOSFET comprising a source coupled to the power net, a drain coupled to the output, and a gate coupled to the second input;
a third p-type MOSFET comprising a source coupled to the power net, a drain coupled to the output, and a gate coupled to the third input;
a fourth p-type MOSFET comprising a source coupled to the power net, a drain, and a gate coupled to the first inverse input;
a fifth p-type MOSFET comprising a source coupled to the drain of the fourth p-type MOSFET, a drain, and a gate coupled to the second inverse input;
and
a sixth p-type MOSFET comprising a source coupled to the drain of the fifth p-type MOSFET, a drain coupled to the inverse output, and a gate coupled to the third inverse input.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/060,162Filed 22 Oct 2013

Priority

17 Jan 2008

Published

5 Jun 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
H03K 19/0033
Modifications for increasing the reliability for protection: radiation hardening

Family

Application61/011,599Us provisional application · filed 17 Jan 2008

Application61/011,989Us provisional application · filed 22 Jan 2008

Application61/068,483Us provisional application · filed 7 Mar 2008

Application61/123,003Us provisional application · filed 5 Apr 2008

Application12/354,655Continuation in part · filed 15 Jan 2009

Application61/630,008Us provisional application · filed 2 Dec 2011

Application13/463,688Continuation in part · filed 3 May 2012

Application61/795,654Us provisional application · filed 22 Oct 2012

Application13/692,800Continuation in part · filed 3 Dec 2012

Application61/806,651Us provisional application · filed 29 Mar 2013

Application14/060,162Continuation in part

US 2009/0184733 A1Published application

US 2013/0038348 A1Published application

US 2013/0162293 A1Published application

US 9,083,341 B2Related patent

US 2014/0157223 A1This patent

From the US filing history. Foreign family members aren’t listed.

Circuit and layout design methods and logic cells for soft error hard integrated circuits

Life of this patent

Circuit and layout design methods and logic cells for soft error hard integrated circuits

Life of this patent

Abstract

Claims21