Layout design apparatus and layout design method
AssigneeFujitsu Limited
InventorsMasashi Arayama, Yuuki Watanabe
Life of this patent
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Abstract
A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.
Claims18
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A layout design method, comprising:
- executing by a computer operations of:
- calculating a channel count of channels available to lead wiring from a terminal of a macro to a wiring layer based on design data of a hierarchical layout of a multilayer circuit including the macro;
- and
- sequentially calculating a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.
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Dependencies are inferred from the claim text.