Method of generating a set of defect candidates for wafer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMin-Hsin HSIEH, Tsung-Hsien LEE
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Abstract
A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.
Claims22
A method of generating a set of defect candidates for a wafer, the wafer comprising at least one die manufactured according to a mask, the mask being prepared by combining a plurality of layout areas, the method comprising:
- generating, by a hardware processor, a filtration area according to a graph operation of one or more of the plurality of layout areas;
- and
- generating the set of defect candidates having positions outside the filtration area,
- wherein the plurality of layout areas comprises a layout area including a layout design of a digital circuit clock, an analog circuit block, a memory circuit block, a power-device circuit block, or an intellectual property (IP) circuit block.
(canceled)
A non-transitory computer readable storage medium encoded with a computer program code, the computer program code being arranged to cause a hardware processor to:
- generate a filtration area for a wafer manufactured based on a mask, the mask including a plurality of layout areas;
- and
- generate a set of filtered defect candidates by filtering out a subset of initial defect candidates located within the filtration area,
- wherein the plurality of layout areas comprises a layout area including a layout design of a digital circuit clock, an analog circuit block, a memory circuit block, a power-device circuit block, or an intellectual property (IP) circuit block.
A method of generating a boundary area between a first layout area and a second layout area of a mask, a first peripheral edge of the first layout area being arranged to be adjacent to the second layout area on the mask, the method comprising:
- expanding, by a hardware processor, the first layout area by shifting the first peripheral edge of the first layout area outwardly by a first predetermined distance;
- and
- generating the boundary area by subtracting the first layout area from the expanded first layout area,
- wherein the first layout area or the second layout area comprises a layout design of a digital circuit clock, an analog circuit block, a memory circuit block, a power-device circuit block, or an intellectual property (IP) circuit block.
Dependencies are inferred from the claim text.