Low power scan & delay test method and apparatus

A process of delay testing logic circuitry, comprising:

• A. enabling shifting of parallel connected, equal length subdivisions of a divided scan path;
• B. shifting sequentially and separately respective portions of a test pattern of stimulus bits, originally produced for a contiguous scan path, from a single lead through each of the parallel connected, equal length subdivisions of a divided scan path;
• C. applying the stimulus bits from each subdivision of the divided scan path to only a part of the logic circuitry connected to that subdivision while shifting the stimulus bits, the applying causing the logic circuitry of that part to produce binary state response bits, and the shifting of stimulus bits through that subdivision causing the response bits from only that part to change binary states;
• D. capturing simultaneously in all subdivisions of the scan path from all of the parts of the logic circuitry first response bits occurring in response to a previous shift of stimulus bits in each subdivision;
• E. capturing simultaneously in all subdivisions of the scan path from all of the parts of the logic circuitry second response bits occurring in response to applying the first response bits as stimulus bits to the logic circuitry;
• and
• F. separately and sequentially shifting the captured second response bits from the subdivisions to a single lead of the scan path.