Selectively accessing test access ports in a multiple test access port environment

An integrated circuit comprising:

• A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;
• B. first test access port circuitry having a test data input coupled to the test data in lead, a test data output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the first test access port circuitry having a first enable input and having a first select output;
• C. second test access port circuitry having a test data input coupled to the test data in lead, a test data output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the second test access port circuitry having a second enable input and having a second select output;
• and
• D. linking module circuitry having a test data input coupled to the test data in lead, a test data output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the linking module circuitry having a first enable output connected to the first enable input and a second enable output connected to the second enable input, the linking module circuitry including:
• i. a first gate having a first select input connected to the first select output, a first enable input connected to the first enable output, and a first output;
• and
• ii. a second gate having a second select input connected to the second select output, a second enable input connected to the second enable output, and a second output.