Method and system for providing a smart memory architecture

A method for providing a bit error rate built-in self test on a memory device, the method comprising:

• performing, by the memory device, at least one of a write error rate built-in self test and a read error rate built-in self test;
• analyzing results of the at least one of the write error rate built-in self test and the read error rate built-in self test;
• and
• automatically adjusting one or more test parameters responsive to the analysis.

A memory device, comprising:

• bit error rate control logic configured to control a bit error rate built-in self test;
• an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;
• a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test;
• and
• a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test.

A system for providing a bit error rate built-in self test, comprising:

• a bus;
• a memory coupled to the bus;
• and
• a smart memory controller, including:
• bit error rate control logic configured to control a bit error rate built-in self test;
• an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;
• a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test;
• and
• a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test.