Memory subsystem command bus stress testing

An electronic device comprising:

• a memory subsystem including
• a memory device to store data and execute memory device commands to access and manage the data;
• a memory controller coupled to the memory device via a data bus and via a command bus, the memory controller to drive the command bus with memory device commands;
• and
• a buffer coupled to the command bus, the buffer including logic to detect that the at least a portion of the command bus is in a state where the memory controller does not drive the portion with a valid executable memory device command, generate a signal pattern in response to detecting the state, the signal pattern generated based on the detected state, and inject the signal pattern on the command bus after a scheduler of the memory controller to drive the portion of the command bus with the signal pattern;
• and
• a touchscreen display coupled to generate a display based on data stored in the memory subsystem.

A method comprising:

• detecting that at least a portion of command signal on a command bus between a memory controller and a memory device is in a state where the memory controller does not drive the portion with a valid executable memory device command;
• generating a signal pattern in response to detecting the state, the signal pattern generated based on the detected state;
• and
• injecting the signal pattern on the command bus after a scheduler of the memory controller to drive the portion of the command bus with the signal pattern.