Memory subsystem data bus stress testing

A method comprising:

• receiving a test transaction at a memory controller, the test transaction indicating one or more memory I/O (input/output) operations to perform a test on a memory device coupled to the memory controller;
• in response to receiving the test data transaction, generating with a test signal generator of the memory controller, a test data signal pattern, including selecting from multiple different pattern signal generators of the test signal generator that generate different types of signal patterns;
• scheduling the test data signal pattern with a scheduler of the memory controller in accordance with a memory device I/O protocol;
• and
• sending the test data signal pattern to the memory device to cause the memory device to execute an I/O operation to implement a portion of the test transaction.

An electronic device comprising:

• a memory subsystem including
• a memory device to store data and execute memory device commands to access and manage the data;
• a memory controller coupled to the memory device to receive a test transaction, the test transaction indicating one or more memory I/O (input/output) operations to perform a test on a memory device coupled to the memory controller;
• a test signal generator of the memory controller to generate a test data signal pattern in response to the memory controller receiving the test data transaction, the test signal generator including multiple different pattern signal generators to generate different types of signal patterns;
• and
• a scheduler of the memory controller to schedule the test data signal pattern in accordance with a memory device I/O protocol, and sending the test data signal pattern to the memory device to cause the memory device to execute an I/O operation to implement a portion of the test transaction;
• and
• a touchscreen display coupled to generate a display based on data stored in the memory subsystem.