Implementing dram failure scenarios mitigation by using buffer techniques delaying usage of ras features in computer systems

A system for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques in a computer system comprising:

• a memory including dynamic random access memory (DRAM);
• a memory controller coupled to said memory;
• a buffer provided with said memory controller;
• said memory controller, analyzing address range of identified physical address data read/write failures;
• said memory controller, identifying predefined failure types for the identified physical address data read/write failures, and
• said memory controller, using said buffer to selectively store and retrieve data, responsive to identified predefined failure types.