Back to results
US 2014/0157043 A1Published application
Memories utilizing hybrid error correcting code techniques
OwnerJoshua D. Ruggieroinventor
Life of this patent
Estimating the term…
Abstract
Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of a memory for which ECC techniques are applied or a second region of the memory for which ECC techniques are not applied. The memory access is processed utilizing ECC techniques if the address corresponds to the first region of the memory and processed without utilizing the ECC techniques if the address corresponds to the second region of the memory.
Claims20
A system comprising:
- memory devices to provide data storage corresponding to a range of memory addresses, a first portion of the memory addresses are protected by an error correcting code (ECC) technique and a second portion of the memory addresses are not protected by the ECC technique;
- a memory control device coupled with the memory devices, the memory control device having a plurality of processing paths, wherein a first set of the processing paths operate to apply the ECC technique to data and a second set of the processing paths operate to cause the data to be stored without applying the ECC technique, the memory control device to selectively apply the ECC technique based on an address corresponding to a memory access request.
A method comprising:
- receiving a memory access request having an associated address;
- determining whether the address corresponds to a first region of a memory for which error correcting code (ECC) techniques are applied or a second region of the memory for which ECC techniques are not applied;
- processing the memory access utilizing ECC techniques if the address corresponds to the first region of the memory;
- processing the memory access without utilizing the ECC techniques if the address corresponds to the second region of the memory.
1 more element
An apparatus comprising:
- a first interface to communicate with processing circuitry;
- a second interface to communicate with memory devices;
- control circuitry coupled with the first interface and the second interface, the control circuitry to receive a memory access request having an associated address via the first interface, to determine whether the address corresponds to a first region of a memory for which error correcting code (ECC) techniques are applied or a second region of the memory for which ECC techniques are not applied, to process the memory access utilizing ECC techniques if the address corresponds to the first region of the memory, and to process the memory access without utilizing the ECC techniques if the address corresponds to the second region of the memory.
Dependencies are inferred from the claim text.