US 2014/0157021 A1 · ENFORCING A POWER CONSUMPTION DUTY CYCLE IN A PROCESSOR

Abstract

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Claims26

Dependent claims

A processor comprising:

a plurality of cores each to independently execute instructions;
and
a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor, the PCU including a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period.

A system comprising:

a multicore processor comprising:
a plurality of cores each to independently execute instructions;
a plurality of graphics engines each to independently perform graphics operations;
and
a power control unit (PCU) coupled to the plurality of cores to control power consumption of the multicore processor, the PCU including a control logic to allow a power consumption level of the multicore processor to be above a defined power limit for a portion of an operating period, the portion corresponding to a duty cycle value stored in a configuration storage of the multicore processor;
a power supply unit coupled to the multicore processor to provide a regulated voltage to the multicore processor;
and
a dynamic random access memory (DRAM) coupled to the multicore processor.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/997,295Filed 30 Nov 2012

Published

5 Jun 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 1/3234
Power management, i.e. event-based initiation of a power-saving mode: power saving characterised by the action undertaken
G06F 1/324
Power saving characterised by the action undertaken: by lowering clock frequency
G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
G06F 8/4432
Optimisation: reducing the energy consumption

Enforcing a power consumption duty cycle in a processor

Life of this patent

Enforcing a power consumption duty cycle in a processor

Life of this patent

Abstract

Claims26