Processor and control method of processor

A control method of a processor comprising:

• fetching an instruction from an instruction address defined as an instruction storage source at a fetching stage of a processor repeating an instruction process including the fetching stage of fetching the instruction and an execution stage of executing the instruction;
• registering, in an associative relation storage unit, an associative relation between a high-order bit field of the instruction address of the instruction undergoing the instruction process and high-order address information into which the high-order bit field of the instruction address is encoded;
• encoding the high-order bit field contained in the instruction address into the high-order address information on the basis of the associative relation;
• decoding the high-order bit field from the high-order address information on the basis of the associative relation;
• and
• predicting whether an instruction fetched by the instruction fetch unit is a branch instruction or not on the basis of history information to store the high-order address information and a low-order bit field associated with a branch destination address of the branch instruction undergoing the instruction process.