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US 2014/0156972 A1Published application
Control Transfer Termination Instructions Of An Instruction Set Architecture (ISA)
AssigneeIntel Corporation
InventorsVedyvas Shanbhogue, Jason W. Brandt, Uday R. Savagaonkar, Ravi L. Sahita
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Abstract
In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
Claims30
A processor comprising:
- a fetch unit to fetch instructions;
- a decode unit to decode the instructions, the decode unit including a control transfer termination (CTT) logic, responsive to a control transfer instruction, to decode the control transfer instruction into a decoded control transfer instruction;
- an execution unit to execute decoded instructions;
- and
- a retirement unit to retire the decoded control transfer instruction, wherein the retirement unit is to raise a fault if a next instruction to be retired after the decoded control transfer instruction is not a CTT instruction.
2 more elements
A processor comprising:
- an execution logic to execute instructions;
- and
- a control transfer termination (CTT) logic coupled to the execution logic, wherein the CTT logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- decoding a control transfer instruction and decoding a next instruction following the control transfer in a decode unit of a processor;
- providing the control transfer instruction and the next instruction to a pipeline of the processor;
- retiring the control transfer instruction in a retirement unit of the processor;
- and
- raising a fault via the retirement unit, if the next instruction is not a control transfer termination (CTT) instruction.
2 more elements
A system comprising:
- a processor including a front end unit having a control transfer termination (CTT) logic, an execution logic coupled to the front end unit to execute instructions, and a retirement unit coupled to the execution logic, wherein the retirement unit is to raise a CTT fault when a target instruction of a retired control transfer instruction is not a CTT instruction;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
Dependencies are inferred from the claim text.