Verification of a vector execution unit design
AssigneeInternational Business Machines Corporation
InventorsMAARTEN J. BOERSMA, UDO KRAUTZ, ULRIKE SCHMIDT
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Abstract
A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.
Claims6
A method for verification of a vector execution unit design, the method comprising the steps of:
- issuing an instruction into a first instance of a vector execution unit;
- issuing the instruction into a second instance of the vector execution unit;
- issuing a random operand into a first lane of the first instance of the vector execution unit;
- issuing the random operand into a second lane of the second instance of the vector execution unit;
- receiving results from execution of the instruction and the random operand in the first instance of the vector execution unit and results from execution of the instruction and the random operand in the second instance of the vector execution unit;
- and
- comparing the received results.
Dependencies are inferred from the claim text.