System and method for achieving enhanced performance with multiple networking central processing unit (cpu) cores

A network device having a symmetric multiprocessing architecture, the network device comprising:

• a dedicated CPU core;
• a plurality of CPU cores;
• a network interface to receive one or more data packets;
• a memory whose access is shared by the dedicated CPU core and the plurality of CPU cores,
• wherein the memory comprises a data structure that is specific to each of the CPU cores, and
• wherein a value of the data structure corresponding to a particular CPU core among the plurality of CPU cores is updated without using any locking mechanism in response to receiving a data packet by the particular CPU core.

A non-transitory computer-readable storage medium storing embedded instructions for a plurality of operations that are executed by one or more mechanisms implemented within a network device having a symmetric multiprocessing architecture, the plurality of operations comprising:

• storing a data structure, which is specific to each of the CPU cores, in a memory shared by the plurality of CPU cores;
• and
• allocating a dedicated CPU core in the network device having the symmetric multiprocessing architecture to process only data packets received from other CPU cores in the network device having the symmetric multiprocessing architecture;
• receiving, by the dedicated CPU core, a query corresponding to one or more of the other CPU cores;
• retrieving, by the dedicated CPU core, one or more data values at one or more memory locations in the shared memory storing data for the one or more CPU cores corresponding to the query;
• and
• aggregating, by the dedicated CPU core, the one or more retrieved data values to generate an aggregated data value;
• and
• responding, by the dedicated CPU core, to the query based on the aggregated data value.