Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput

A processor unit configured to perform a method for supporting a plurality of requests for access to a data cache memory, said method comprising:

• accessing a first plurality of requests to access said data cache memory, wherein said data cache memory comprises a plurality of blocks;
• responsive to said first plurality of requests to access said data cache memory, accessing a tag memory that maintains a plurality of copies of tags for each entry in said data cache memory and identifying tags that correspond to individual requests of said first plurality of requests;
• and
• performing arbitration in a same clock cycle as said accessing said tag memory and said identifying tags, wherein said arbitration comprises:
• identifying a second plurality of requests to access said data cache memory from said first plurality of requests, wherein said second plurality of requests accesses a same block in a same cache-line within said data cache memory;
• and
• selecting each request from said second plurality of requests to receive data from said same block.

A computer system comprising:

• a memory;
• a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order;
• and
• a cache system, comprising:
• a data cache memory configured to store blocks of data;
• a tag memory configured to stored tags that correspond to said blocks of data;
• and
• a cache controller operable to implement a method for supporting a plurality of requests for access to a data cache memory, said method comprising:
• accessing a first plurality of requests to access said data cache memory, wherein said data cache memory comprise a plurality of blocks;
• responsive to said first plurality of requests to access said data cache memory, accessing a tag memory that maintains a plurality of copies of tags for each entry in said data cache memory and identifying tags that correspond to individual requests of said first plurality of requests;
• and
• performing arbitration in a same clock cycle as said accessing said tag memory and said identifying tags, wherein said arbitration comprises:
• identifying a second plurality of requests to access said data cache memory from said first plurality of requests, wherein said second plurality of requests accesses a same block in a same cache-line within said data cache memory;
• and
• selecting each request from said second plurality of requests to receive data from said same block.