Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System

A non-transitory machine readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• receiving a page fault from a device processor coupled to a device memory, the device processor coupled to a host processor coupled to a host memory, the device processor and the host processor asymmetrically sharing a virtual memory space;
• sending a request from the device processor to the host processor for a page associated with the page fault;
• and
• receiving the page by the device processor from the host processor as a page size unit, and wherein the page is locked in the host memory if the page is indicated to be write permissible.

A system comprising:

• a multicore processor including:
• a core having a translation lookaside buffer (TLB) to store first virtual address to physical address translations for a memory;
• and
• a graphics processor coupled to the core via an interconnect and including a graphics translation lookaside buffer (gTLB) to store second virtual address to physical address translations for a graphics memory;
• the memory coupled to the multicore processor to store a first plurality of pages each corresponding to a physical address of the memory;
• and
• the graphics memory coupled to the multicore processor to store a second plurality of pages each corresponding to a second physical address of the graphics memory, wherein the core and the graphics processor have a shared virtual address space, and in response to a page fault associated with a first request to the graphics memory for a page, the graphics processor is to transmit a second request for the page to the core and the core is to provide the page to the graphics processor from the memory.