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US 2014/0156933 A1Published application
System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions
AssigneeIntel Corporation
InventorsOmar M. Shaikh, Ravi Rajwar, Paul Caprioli, Muawya M. Al-Otoom
Life of this patent
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Abstract
Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.
Claims19
An apparatus comprising:
- logic to assign a transactional memory (TM) region indicator to each instruction of a transaction;
- execution logic to execute each instruction of the transaction;
- a copy-on-write (COW) buffer to maintain a mapping from checkpointed architectural registers to physical registers, wherein the COW maintains a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW of the last committed instruction, a second pointer to identify a boundary between a youngest TM region and a currently retiring position, and a retirement pointer to identify a currently retiring instruction;
- and
- a data cache to store data associated with executed instructions, wherein each entry of the data cache has a read-bit per TM region indicator to mark memory state of speculative reads wherein a read-bit for a TM region is set when data is speculatively read from that cache line during that transaction and a write-bit to indicate when the cache line has speculatively written data.
2 more elements
A method comprising:
- assigning a transactional memory (TM) region indicator to each instruction of a transaction;
- storing previously used physical registers associated with the transaction into a copy-on-write (COW) buffer, wherein the COW maintains a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW of the last committed instruction, a second pointer to identify a boundary between a youngest TM region and a currently retiring position, and a retirement pointer to identify a currently retiring instruction;
- executing the instructions of the transaction;
- retiring one or more oldest load instructions of each TM region from a reorder buffer until a first instruction of an oldest TM region that is not in an initial grouping from that TM region is reached until the oldest TM region has committed;
- and
- setting a read-bit for each load that has been retired into a corresponding data cache entry.
3 more elements
A method comprising:
- assigning a transactional memory (TM) region indicator to each instruction of a transaction;
- executing the instructions of the transaction;
- retiring one or more store instructions of the transaction from a store buffer until a last store of an oldest TM region is retired and halting retirement of any other stores until the oldest TM region has committed;
- and
- setting a write-bit for each store that has been retired into a corresponding data cache entry.
2 more elements
Dependencies are inferred from the claim text.