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US 2014/0156907 A1Published application
Smart memory
AssigneeThe Intellisis Corporation
InventorDouglas A. Palmer
Life of this patent
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Abstract
Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets.
Claims13
An on-chip processing system comprising:
- a memory bank configured to store packets of information, wherein an individual packet includes a packet header and a packet payload, wherein the packet header includes one or more operator codes;
- an interconnect module configured to receive packets from individual ones of a set of interconnect sources, wherein the set of interconnect sources includes a controller and the memory bank, wherein the interconnect module is further configured to transfer packets to individual ones of a set of interconnect destinations, wherein the set of interconnect destinations includes the controller and an external device, wherein transfer of individual packets is guided by one or more operator codes therein;
- the controller configured to receive packets from the interconnect module and further configured to transfer packets to individual ones of a set of controller destinations, wherein the set of controller destinations includes a first processing engine, a second processing engine, and the interconnect module, and wherein transfer of individual packets is guided by one or more operator codes therein;
- and
- multiple processing engines including the first processing engine and the second processing engine, wherein an individual one of the multiple processing engines is configured to generate, responsive to receiving one or more packets from the controller, output packets by processing the one or more received packets, wherein individual ones of the generated output packets include an output packet header, the output packet header including one or more operator codes,
- wherein the controller is further configured to receive the output packets from individual ones of the processing engines, and wherein the controller is further configured to transfer the output packets, based on one or more operator codes therein, to individual ones of the set of controller destinations.
3 more elements
An on-chip processing system comprising:
- multiple memory banks including a first memory bank and a second memory bank, wherein an individual one of the multiple memory banks is configured to store packets of information, wherein an individual packet includes a packet header and a packet payload, wherein the packet header includes one or more operator codes;
- an interconnect module configured to receive packets from individual ones of a set of interconnect sources, wherein the set of interconnect sources includes a controller, the first memory bank, and the second memory bank, wherein the interconnect module is further configured to transfer packets to individual ones of a set of interconnect destinations, wherein the set of interconnect destinations includes the controller and an external device, wherein transfer of individual packets is guided by one or more operator codes therein;
- the controller configured to receive packets from the interconnect module and further configured to transfer packets to individual ones of a set of controller destinations, wherein the set of controller destinations includes a first processing engine and the interconnect module, and wherein transfer of individual packets is guided by one or more operator codes therein;
- and
- the first processing engine configured to generate, responsive to receiving a first packet and a second packet from the controller, wherein the first packet originates from the first memory bank and the second packet originates from the second memory bank, one or more output packets based on the first packet and the second packet, wherein individual ones of the one or more output packets include an output packet header, the output packet header including one or more operator codes,
- wherein the controller is further configured to receive the output packets from the first processing engine, and wherein the controller is further configured to transfer the output packets, based on one or more operator codes therein, to individual ones of the set of controller destinations.
3 more elements
A method to process packets of information, the method being implemented in a system that includes a memory bank, an interconnect module, a controller, and multiple processing engines, the method comprising:
- storing packets of information, wherein an individual packet includes a packet header and a packet payload, wherein the packet header includes one or more operator codes;
- receiving, by the interconnect module, packets from individual ones of a set of interconnect sources, wherein the set of interconnect sources includes the controller and the memory bank;
- transferring, by the interconnect module, packets to individual ones of a set of interconnect destinations, wherein the set of interconnect destinations includes the controller and an external device, wherein transfer of individual packets is guided by one or more operator codes therein;
- receiving, by the controller, packets from the interconnect module;
- transferring, by the controller, packets received from the interconnect module to individual ones of a set of controller destinations, wherein the set of controller destinations includes a first processing engine, a second processing engine, and the interconnect module, and wherein transfer of individual packets is guided by one or more operator codes therein;
- receiving, by a first processing engine, one or more packets from the controller;
- generating, by the first processing engine, responsive to receiving one or more packets from the controller, output packets by processing the one or more received packets, wherein individual ones of the generated output packets include an output packet header, the output packet header including one or more operator codes;
- transferring, by the first processing engine, the output packets to the controller;
- receiving, by the controller, the output packets from the first processing engine;
- and
- transferring, by the controller, the received individual output packets to individual ones of the set of controller destinations based on one or more operator codes included in the received individual output packets.
8 more elements
Dependencies are inferred from the claim text.