Can bus edge timing control apparatus, systems and methods

A system to exercise controller area network (CAN) bus dominant-to-recessive transmit data (TxD) bit timing control, comprising:

• a CAN bus transceiver to send differential signals on a CAN bus and to exercise control of a CAN bus impedance;
• a CAN bus node controller to assemble transmit data (TxD) frames for transmission to another bus node on the CAN bus and to selectively activate a flexible data rate (FD) signal line;
• a main CAN node physical layer (PHY) differential driver portion of the CAN bus transceiver to drive the CAN bus to an active state upon receipt of a dominant TxD bit in a CAN TxD frame received from the CAN bus node controller;
• and
• at least one recessive nulling fractional differential driver portion of the CAN bus transceiver output-coupled in parallel with the main CAN node PHY differential driver circuit to perform a recessive nulling operation by entering a conductive state and inserting a recessive nulling impedance in parallel with a differential output of the main CAN node PHY differential driver circuit across the CAN bus for a selected recessive nulling time period during a recessive bit time period associated with at least one recessive data bit in the CAN TxD frame in order to increase a rate of decay of a CAN bus dominant-to-recessive differential signal waveform associated with a dominant-to-recessive data bit transition.