Functional built-in self test for a chip

A method for self-testing a functional logic module on a chip, the functional logic module for performing a selected application, the chip comprising a primary interface for the functional logic module, a secondary interface for the functional logic module, an input interface protocol generator coupled to the primary interface, an output interface protocol payload checker coupled to the primary interface and an emulator engine coupled to the secondary interface, the method comprising:

• generating, by the input interface protocol generator, patterns to be inserted into the primary interface, wherein the patterns are configured to test a function of the functional logic module that utilize the secondary interface;
• executing, by the functional logic module, the patterns inserted into the primary interface;
• receiving, by the emulator engine, an output from the secondary interface based on the inserted patterns executed by the functional logic module;
• determining that the output received by the emulator engine from the secondary interface is correct;
• transmitting test communications from the emulator engine to the functional logic module via the secondary interface, the test communications being transmitted based on the output received by the emulator engine, the emulator engine allowing testing of the function when a secondary device is not coupled to the secondary interface of the functional logic module;
• generating, by the functional logic module, a response based on the test communications received by the functional logic module, wherein the response is provided to the primary interface;
• and
• determining, by the output interface protocol payload checker, that the response is correct by comparing the response to an expected result.

A self-test system integrated on a chip, the chip comprising a functional logic module for performing a selected application, the self-test system comprising:

• a primary interface to the functional logic module, the primary interface configured to interface with a primary device;
• an input interface protocol generator for generating commands to be inserted into the primary interface, wherein the functional logic module arbitrates placement of each of the commands for execution of the commands in parallel;
• a secondary interface to the functional logic module, the primary interface configured to interface with a secondary device, the functional logic module generating an input for the secondary interface based on the commands;
• an emulator engine coupled to the secondary interface, the emulator engine configured to test a function of the functional logic module based on the input received from the secondary interface, wherein the emulator engine is further configured to test the function when the secondary device is not coupled to the chip and wherein the emulator engine provides an output to the secondary interface based on testing of the function;
• and
• an output interface protocol payload checker coupled to the primary interface for determining that a response received from the primary interface is correct by comparing the response to an expected result, the response provided by the functional logic module based on the output received generated by the emulator engine, wherein the emulator engine, the input interface protocol generator and the output interface protocol payload checker enable the functional logic module to execute the inserted patterns at a maximum operational frequency.