US 2014/0154880 A1 · Post-Polymer Revealing of Through-Substrate Via Tips

Abstract

A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.

Claims11

Dependent claims

A method of forming semiconductor die while reducing copper (CU) contamination, comprising:

forming a layer of polymer or a precursor of said polymer on a bottomside of a substrate having a topside including active circuitry, and a plurality of through substrate vias (TSVs), said TSVs having a liner comprising at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from said bottomside, wherein said layer of said polymer or said precursor and said liner cover said plurality of TSV tips and said layer of said polymer or said precursor is between said plurality of TSV tips on said bottomside, and
removing said polymer or said precursor and said liner over a top of said TSV tips to reveal said metal core, wherein after said removing said polymer or said precursor remains on said bottomside between said TSV tips.

Dependencies are inferred from the claim text.

Facts

Application

14/173,067Filed 5 Feb 2014

Priority

9 Sep 2011

Published

5 Jun 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0245
The interconnections being through-semiconductor vias: comprising use of blind vias during the manufacture
H10W 20/0249
The interconnections being through-semiconductor vias: wherein the through-semiconductor via protrudes from backsides of the chips, wafers or…

Post-Polymer Revealing of Through-Substrate Via Tips

Life of this patent

Post-Polymer Revealing of Through-Substrate Via Tips

Life of this patent

Abstract

Claims11