US 2014/0154878 A1 · NOR FLASH DEVICE MANUFACTURING METHOD

Abstract

An embodiment of a NOR Flash device manufacturing method is disclosed, which includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method of the present invention improves the yield of the NOR Flash device.

Claims20

Dependent claims

A method of manufacturing a NOR Flash device, comprising:

providing a substrate having a first polycrystalline silicon layer disposed thereon;
forming a first hard mask layer on the first polycrystalline silicon layer;
etching the first hard mask layer to form a first opening using a dry etching process, and cleaning a gas pipeline connected to an etching cavity prior to etching the first hard mask layer;
forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer covers a bottom and a side wall of the first opening;
etching the second hard mask layer to form a second opening using a self-aligning process, wherein a width of the second opening is smaller than a width of the first opening;
and
etching the first polycrystalline silicon layer to form a floating gate using the self-aligning process.

4 more elements

A method of manufacturing a NOR Flash device, comprising:

providing a substrate having a first polycrystalline silicon layer disposed thereon;
forming a first hard mask layer on the first polycrystalline silicon layer;
etching the first hard mask layer to form a first opening using a dry etching process, and cleaning a gas pipeline connected to an etching cavity prior to etching the first hard mask layer;
forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer covers a bottom and a side wall of the first opening;
etching the second hard mask layer to form a second opening, wherein a width of the second opening is smaller than a width of the first opening;
and
etching the first polycrystalline silicon to form a floating gate.

4 more elements

Dependencies are inferred from the claim text.

Nor flash device manufacturing method

Life of this patent

Nor flash device manufacturing method

Life of this patent

Abstract

Claims20