Methods for fabricating integrated circuits having low resistance metal gate structures

A method for fabricating an integrated circuit, the method comprising:

• forming a metal gate stack in a FET trench formed in a FET region that comprises an interlayer dielectric material on a semiconductor substrate;
• etching the metal gate stack to form a recessed metal gate stack and a recess that is defined by sidewalls in the FET region and that is disposed along an upper section of the FET trench above the recessed metal gate stack;
• forming a liner overlying the sidewalls and the recessed metal gate stack and defining an inner cavity in the recess;
• depositing a copper seed layer overlying the liner;
• reflowing the copper seed layer to form a reflowed copper seed layer that partially fills the inner cavity;
• etching the reflowed copper seed layer to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity;
• and
• electrolessly depositing copper on the copper portion to fill a remaining portion of the inner cavity.

A method for fabricating an integrated circuit, the method comprising:

• forming a metal gate stack in a FET trench formed in a FET region that comprises an interlayer dielectric material on a semiconductor substrate;
• etching the metal gate stack to form a recessed metal gate stack and a recess that is defined by sidewalls in the FET region and that is disposed along an upper section of the FET trench above the recessed metal gate stack;
• forming a liner overlying the sidewalls and the recessed metal gate stack and defining an inner cavity in the recess;
• filling the inner cavity with copper to define a copper fill;
• etching the copper fill to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity;
• and
• electrolessly depositing copper on the copper portion to fill a remaining portion of the inner cavity.